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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad1991 class d/1-bit audio power output stage functional block diagrams 2-channel mode ina inb left input level shifter and switch control h-bridge agnd dgnd av dd dv dd pv dd test control pgnd a1 a2 b1 b2 c1 c2 d1 d2 outa 3 outb 3 outc 3 outd 3 inc ind right input clk r st / pdn mute current overload thermal shutdown thermal warning data loss 2 14 4 6 thermal protection short-circuit protection mute control n 4-channel mode ina inb level shifter and switch control h-bridge agnd dgnd av dd dv dd pv dd test control pgnd a1 a2 b1 b2 c1 c2 d1 d2 inc ind clk r st / pdn mute current overload thermal shutdown thermal warning data loss 2 4 14 6 thermal protection short-circuit protection mute control n outa 3 load requiring dc voltage supply outd 3 load requiring dc voltage supply outb 3 outc 3 features class d/1-bit audio power output stage 5 v analog and digital supply voltages power stage power supply 8 v to 20 v output power @ 0.1% thd + n stereo mode 2 20 w @ 4 @ 14.4 v 2 20 w @ 8 @ 20 v mono mode 1 40 w @ 4 @ 20 v r on < 320 m (per transistor) efficiency > 85% @ full power/8 clickless mute function turn-on and turn-off pop suppression short-circuit protection overtemperature protection data loss protection 2-channel btl outputs or 4-channel single-ended outputs 52-lead exposed pad tqfp package low cost dmos process applications pc audio systems minicomponents automotive amplifiers home theater systems televisions general description the ad1991 is a 2-channel btl or 4-channel single-ended class d audio power output stage. the part is configured during reset to be in either 2-channel mode or 4-channel mode. to protect the ic as well as the connected speakers, the ad1991 provides turn-on and turn-off pop suppression, short-circuit protection, and overtemperature shutdown. to control the ic, a power-down/reset input and a mute pin are available. the output stage can be operated over a power supply range from 8 v to 20 v. in 2-channel mode, transistors a1, b2, c1, and d2 are turned on by a logic 1 on inputs ina and inc, and transistors a2, b1, c2, and d1 are turned on by a logic 0 on inputs ina and inc. in 4-channel mode, transistors a1, b1, c1, and d1 are turned on by a logic 1 on the four inputs, and transistors a2, b2, c2, and d2 are turned on by a logic 0 on the four inputs (see the functional block diagrams).
rev. 0 e2e ad1991especifications 1 parameter min typ max unit test conditions output power p o (f = 1 khz sine wave) 2 20 w r l = 4 ? ? ? ? ? ?/ rst pdn d dd 113 rst pdn p dd 1 rst pdn dd 1 2 d dd 2 p dd 0 00 3 n n dt 20 d dd 12 d dd 0 2 0 2 d 10 rst pdn 20 msu m rst pdn m m rst pdn mpd mute 3 s specifications subject to change without notice. (guaranteed over e40 c to +85 c, av dd = dv dd = 5 v 10%, pv ddx = 20 v 10%, edge speed = slowest, nonoverlap time = shortest.) (av dd = 5 v, dv dd = 5 v, pv ddx = 20 v, ambient temperature = 25 c, load impedance = 8 , unless otherwise noted.)
rev. 0 ad1991 e3e outb outa ina t pdl t pst t nol t pst t pdl t pst t nol t pst figure 1. output timing modex r st / pdn t pdrp t msu t mh figure 2. reset mt ut m m st st m ute mute t
rev. 0 e4e ad1991 absolute maximum ratings 1 (t a = 25 /
rev. 0 ad1991 ? pin configuration 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 ad1991 pgnd1 pgnd1 outa pgnd1 pgnd1 pgnd1 pgnd2 pgnd2 pgnd2 pgnd2 outa outa outb outb outb pv dd1 pv dd1 pv dd1 outc outc outc outd outd outd pv dd2 pv dd2 pv dd2 pgnd1 pgnd1 agnd agnd agnd agnd pgnd2 pgnd2 pgnd2 mode1 mode0 av dd dv dd dgnd err3 err2 err1 err0 ina inb mute rst / pdn clk ind inc pin function descriptions pin no. mnemonic in/out description 1 pgnd1 negative power supply for high power transistors a2 and b2. 2, 3, 4 outa o output of transistor pair a1 and a2. 5, 6, 7 pv dd1 positive power supply for high power transistors a1 and b1. 8, 9, 10 outb o output of transistor pair b1 and b2. 11, 12, 13 pgnd1 negative power supply for high power transistors a2 and b2. 14 err3 i/o edge speed setting msb during reset/active low thermal shutdown error output during normal operation. 15 err2 i/o edge speed setting bit 1 during reset/active low thermal warning error output during normal operation. 16 err1 i/o nonoverlap time setting msb during reset/active thermal low shutdown error output during normal operation. 17 err0 i/o nonoverlap time setting bit 1 during reset/active low data-loss error output or low-side transistor disable input during normal operation. 18 ina i control pin for transistors a1 and a2 always; also control pin for b1 and b2 in 2-channel mode. 19 inb i edge speed setting lsb during reset/during normal operation, control pin for transistors b1 and b2 in 4-channel mode; no function in 2-channel mode. 20 dv dd positive power supply for low power digital circuitry. 21 dgnd negative power supply for low power digital circuitry. 22 mute i active low clickless mute input. 23 inc i control pin for transistors c1 and c2 always; also control pin for d1 and d2 in 2-channel mode. 24 ind i nonoverlap time setting lsb during reset/during normal operation, control pin for transis- tors d1 and d2 in 4-channel mode; no function in 2-channel mode. 25 rst / pdn i active low reset/power-down input. 26 clk i external clock input in external clock mode. 27, 28, 29 pgnd2 negative power supply for high power transistors c2 and d2. 30, 31, 32 outd o output of transistor pair d1 and d2. 33, 34, 35 pv dd2 positive power supply for high power transistors c1 and d1. 36, 37, 38 outc o output of transistor pair c1 and c2. 39, 40, 41, 42 pgnd2 negative power supply for high power transistors c2 and d2. 43, 45, 48, 49 agnd negative power supply for low power analog circuitry. 44 mode0 clock source select (referenced to agnd); normally connected to agnd. 46 av dd positive power supply for low power analog circuitry. 47 mode1 i channel mode select (referenced to agnd). 50, 51, 52 pgnd1 negative power supply for high power transistors a2 and b2.
rev. 0 e6e ad1991 functional description device architecture the ad1991 is an 8-transistor, audio, power output stage. the ad1991 is arranged internally as four transistor pairs that can be used as two h-bridge outputs (2-channel mode) or as four single-ended outputs (4-channel mode), using either two or four ttl compatible inputs to control the transistors. a dead time is automatically provided between the switching of the high- side transistor and low-side transistor when the control inputs change level, to ensure that both the high-side transistor and low-side transistor are never on at the same time. clock source and channel mode selection when the ad1991 is brought out of reset, the logic levels on mode0 and mode1 are latched internally. mode0 determines the internal state machine clock source. mode1 determines the channel mode and the function of err0 t t s s mde0 s 0 1e t m s mde1 m err0 0 2 1 2 e err0 n n 0 t 2 t t r 2 m n ut ut n ut utd m t n t err0 0 1 t err0 t t err0 err0 0 1 e r 1 2 11 13 err2 10 err3 120 err1 t t mute
rev. 0 ad1991 e7e ina inb level shifter and switch control h-bridge agnd dgnd av dd input dv dd pv dd test control pgnd a1 a2 b1 b2 c1 c2 d1 d2 inc ind clk r st / pdn mute current overload thermal shutdown thermal warning data loss 2 4 14 6 thermal protection short-circuit protection mute control n outa 3 outb 3 outc 3 outd 3 figure 4. functional block diagram (1-channel mode) edge speed and nonoverlap settings the ad1991 allows the user to select from one of eight different edge speeds and from one of eight different nonoverlap times. this allows the user to make a trade-off between distortion, efficiency, overshooting at the outputs, and emi. the following sections describe the method used to program the settings. edge speed the edge speed is set by using the three pins, err3 err2 n rst pdn t rst pdn t rst pdn t n n t t e s s err3 err2 e 001 1e 0002 0113 010 101 100 111 110 e err1 err0 nd rst pdn t rst pdn t rst pdn t n nd t n err3 err2 err1 err0 t 300 ? ? ? err1 err0 00 11 00 02 01 13 01 0 10 1 10 0 11 1 11 0
rev. 0 e8e ad1991 application considerations good board layout and decoupling are vital for correct operation of the ad1991. due to the fact that the part switches high currents, there is the potential for large pv dd bounce each time a transis- tor transitions. this can cause unpredictable operation of the part. to avoid this potential problem, close chip decoupling is essen- tial. it is also recommended that the decoupling capacitors be placed on the same side of the board as the ad1991 and connected directly to the pv dd and pgnd pins. by placing the decoupling capacitors on the other side of the board and decoupling through vias, the effectiveness of the decoupling is reduced. this is because vias have inductive properties and, therefore, prevent very fast discharge of the decoupling capacitors. best operation is achieved with at least one decoupling capacitor on each side of the ad1991 or optionally two capacitors per side can be used to further reduce the series resistance of the capacitor. if these decoupling recommendations cannot be followed and decoupling through vias is the only option, the vias should be made as large as possible to increase surface area, thereby reducing inductance and resistance. figures 5 and 6 show two possible layouts to provide close chip decoupling. in both cases, the pv dd to pgnd decoupling is as close as possible to the pins of the ad1991. one solution uses surface-mount capacitors that offer low inductance; however, each output (outa, outb, outc, and outd) must be brought through vias to another layer of the board to be brought to the lc filter. the other solution uses through-hole capacitors that have higher inductance but allow the outputs to connect directly to the lc filter. in this solution, the inductor for outa and outc would span the pv dd trace. these diagrams show four decoupling capacitors from pv dd to pgnd; however, this may not be necessary if capacitors with low series resistance are used. another close chip capacitor is used for av dd to agnd decoupling, w ith the actual power connections to the capacitors being done through vias. this is quite acceptable since av dd is a low current stable supply. finally, a close chip capacitor is used to decouple dv dd to dgnd. this is quite important since dv dd is a digital supply whose current will change dynamically and, therefore, requires good decoupling. for both pv dd and dv dd , additional reservoir capacitors should be used to augment the close chip decoupling, especially for pv dd , which usually has very large transients. thermal considerations careful consideration must be given to heat sinking the ad1991, particularly in applications where the ambient temperature can be much higher than normal room temperature. the three thermal resistances of jc , ca , and ja should be known in order to correctly heat sink the part. these values specify the temperature difference between two points, per unit power dissipation. jc specifies the temperature difference between the junction (die) and the case (package) for each watt of power dissipated in the die. the ad1991 is specified with a jc of 1 / ca , the difference between the case and am bient temperatures, is entirely dependent on the size of heat sink attached to the case, the material used, the method of attach- ment, and the airflow over the heat sink. the value of ca is specified as 26 / ja is the sum of the jc and ca values, and will be between 1 / / ca can be calculated. for an 8 ? 20 w rms continuous pow er, the power dissipated in the ad1991 can be calculated as follows: power supplied to loads = 40 w rms total power supplied to the ad1991 = (40/85 100) = 47 w rms power dissipated in the ad1991 = 7 w rms if the ambient temperature can reach 85 ja requirement of (55/7) = 7.9 / ca of 6.9 /
rev. 0 ad1991 e9e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pv dd plane cap cap cap cap cap cap a gnd plane pgnd plane figure 5. layout using surface-mount capacitors (4 1 6 5 4 3 2 13 12 11 10 9 8 7 16 15 14 26 25 24 23 22 21 20 19 18 17 39 38 37 36 35 34 33 32 40 41 42 43 44 45 46 47 48 49 50 51 52 27 28 29 30 31 pv dd plane cap cap cap cap a gnd plane cap cap pgnd plane figure 6. layout using through-hole capacitors (4
rev. 0 e10e ad1991 pwm_l gnd pwm_r analog input_l gnd analog input_r modulator av dd dv dd feedback agnd dgnd feedback ad1991 av dd dv dd pv dd pv dd agnd dgnd pgnd pgnd av dd agnd dv dd dgnd figure 7. simplified system schematic for analog-in, analog-out system
rev. 0 ad1991 e11e outline dimensions 52-lead thin quad flat package, exposed pad [tqfp/ep] (sv-52) dimensions shown in millimeters 6.50 sq exposed pad 0.65 bsc 0.38 0.32 0.22 12.00 bsc sq 10.00 bsc sq top view (pins down) 40 52 1 14 13 26 27 39 1.20 max view a 0.20 0.09 0.75 0.60 0.45 view a 1.05 1.00 0.95 7 3.5 0 seating plane 0.15 0.05 40 52 1 14 13 26 27 39 bottom view (pins up) compliant to jedec standards ms-026acc with the exception that the exposed die pad shall be coplanar with bottom of package within 0.05 millimeters.

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